This disclosure relates to circuitry for converting data that is input as successive groups of parallel data bit signals, each of the input groups having a first number of data bits, to successive groups of parallel data bit output signals, each of the output groups having a second number of data bits, the second number being different from the first number. Such circuitry may be referred to as data width scaler circuitry. Each bit that goes into such data width scaler circuitry corresponds to one respective bit that comes out of the circuitry. (A “bit” is a binary digit.)
Data width scaler circuitry may be needed in any of a variety of contexts. For example, a received serial data signal may include multidigit payload data bit words that are “padded” with one or more “header” data bits. The header data bits may be used for such purposes and indicating where word boundaries are, parity checking, cyclic redundancy checking, reducing or eliminating possible DC (direct current) bias of the payload data, etc. The receiving circuitry may covert the received serial data signal to successive groups or blocks of parallel data signal bits. These input blocks may include both payload and padding bits, and they must typically be formed at a rate (i.e., a clock signal rate) that keeps pace with the rate at which bits are arriving in the serial data signal. On the other hand, at least some circuitry downstream from the receiver circuitry may need only the payload data, so that one function that may need to be performed between the receiver circuitry and the downstream circuitry is to eliminate the padding bits. This may effectively change the “width” of the data groups as they pass from the receiver circuitry to the downstream circuitry.
Another function that is often thought to be required in an interface between receiver circuitry and downstream circuitry as described above is to change the clock rate between a first clock rate used by the receiver circuitry and a second clock rate used by the downstream circuitry. The receiver circuitry typically needs to operate at a clock rate that is dictated by the rate at which successive bits arrive in the received serial data signal. On the other hand, it is typically preferred to operate at least some of the downstream circuitry at a clock rate that is a function of the rate at which payload data words are present in the received signal. Because of the presence of padding bits in the received serial data signal, fairly complex circuitry may be required to provide both the first clock signal needed by the receiver circuitry, and the second clock signal (having a different frequency from the first clock signal) needed by the downstream circuitry.
As an example of the foregoing, certain industry-standard serial data communication protocols provide two padding bits for every 64 data payload bits. Other industry-standard serial communication protocols provide three padding bits for every 64 data payload bits. Just this small set of examples illustrates two problems. First, the ratio between the serial data receiver circuitry clock signal frequency and the clock signal frequency needed by the more downstream circuitry that deals only with the payload data can be quite complex (e.g., a clock signal frequency ratio that is related to the ratio 66:64 (which is an example of a non-integer ratio) or the ratio 67:64 (which is another example of a ratio that is non-integer). Second, if it is desired to provide circuitry that can support any of several different communication protocols, the differences among such protocols make that quite difficult to do. For example, general-purpose circuitry that can support both 66:64 and 67:64 data width and clock frequency shifts may need to be quite complex. And these are only some examples of the various communication protocols that it may be desirable for relatively general-purpose circuitry to be able to support. Adding more protocol options to the capabilities of such circuitry tends to increase the complexity of the circuitry even more. Some protocols may even require ratios that are non-rational.